Cypress Semiconductor /psoc63 /SAR /SAMPLE_CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SAMPLE_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LEFT_ALIGN)LEFT_ALIGN 0 (UNSIGNED)SINGLE_ENDED_SIGNED 0 (UNSIGNED)DIFFERENTIAL_SIGNED 0AVG_CNT 0 (AVG_SHIFT)AVG_SHIFT 0 (ACCUNDUMP)AVG_MODE 0 (CONTINUOUS)CONTINUOUS 0 (DSI_TRIGGER_EN)DSI_TRIGGER_EN 0 (DSI_TRIGGER_LEVEL)DSI_TRIGGER_LEVEL 0 (DSI_SYNC_TRIGGER)DSI_SYNC_TRIGGER 0 (UNSCHEDULED)UAB_SCAN_MODE 0 (REPEAT_INVALID)REPEAT_INVALID 0VALID_SEL 0 (VALID_SEL_EN)VALID_SEL_EN 0 (VALID_IGNORE)VALID_IGNORE 0 (TRIGGER_OUT_EN)TRIGGER_OUT_EN 0 (EOS_DSI_OUT_EN)EOS_DSI_OUT_EN

SINGLE_ENDED_SIGNED=UNSIGNED, AVG_MODE=ACCUNDUMP, DIFFERENTIAL_SIGNED=UNSIGNED, UAB_SCAN_MODE=UNSCHEDULED

Description

Sample control register.

Fields

LEFT_ALIGN

Left align data in data[15:0], default data is right aligned in data[11:0], with sign extension to 16 bits if the channel is differential.

SINGLE_ENDED_SIGNED

Output data from a single ended conversion as a signed value

0 (UNSIGNED): Default: result data is unsigned (zero extended if needed)

1 (SIGNED): result data is signed (sign extended if needed)

DIFFERENTIAL_SIGNED

Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NEG_ADDR_EN is set to 1

0 (UNSIGNED): result data is unsigned (zero extended if needed)

1 (SIGNED): Default: result data is signed (sign extended if needed)

AVG_CNT

Averaging Count for channels that have averaging enabled (AVG_EN). A channel will be sampled (1<<(AVG_CNT+1)) = [2…256] times.

  • In ACCUNDUMP mode (1st order accumulate and dump filter) a channel will be sampled back to back, the average result is calculated and stored and then the next enabled channel is sampled. If shifting is not enabled (AVG_SHIFT=0) then the result is forced to shift right so that is fits in 16 bits, so right shift is done by max(0,AVG_CNT-3).
  • In INTERLEAVED mode one sample is taken per triggered scan, only in the scan where the final averaging count is reached a valid average is calculated and stored in the RESULT register (by definition the same scan for all the channels that have averaging enabled). In all other scans the RESULT register for averaged channels will have an invalid result and the intermediate accumulated value is stored in the 16-bit WORK register. In this mode make sure that the averaging count is low enough to ensure that the intermediate value does not exceed 16-bits otherwise the MSBs will be lost. So for a 12-bit resolution the averaging count should be set to 16 or less (AVG_CNT=<3).
AVG_SHIFT

Averaging shifting: after averaging the result is shifted right to fit in 12 bits.

AVG_MODE

Averaging mode, in DSI mode this bit is ignored and only AccuNDump mode is available.

0 (ACCUNDUMP): Accumulate and Dump (1st order accumulate and dump filter): a channel will be sampled back to back and averaged

1 (INTERLEAVED): Interleaved: Each scan (trigger) one sample is taken per channel and averaged over several scans.

CONTINUOUS
  • 0: Wait for next FW_TRIGGER (one shot) or hardware trigger (e.g. from TPWM for periodic triggering) before scanning enabled channels.
  • 1: Continuously scan enabled channels, ignore triggers.
DSI_TRIGGER_EN
  • 0: firmware trigger only: disable hardware trigger tr_sar_in.
  • 1: enable hardware trigger tr_sar_in (e.g. from TCPWM, GPIO or UDB).
DSI_TRIGGER_LEVEL
  • 0: trigger signal is a pulse input, a positive edge detected on the trigger signal triggers a new scan.
  • 1: trigger signal is a level input, as long as the trigger signal remains high the SAR will do continuous scans.
DSI_SYNC_TRIGGER
  • 0: bypass clock domain synchronisation of the trigger signal.
  • 1: synchronize the trigger signal to the SAR clock domain, if needed an edge detect is done in the peripheral clock domain.
UAB_SCAN_MODE

Select whether UABs are scheduled or unscheduled. When no UAB is scanned this selection is ignored.

0 (UNSCHEDULED): Unscheduled UABs: one or more of the UABs scanned by the SAR is not scheduled, for each channel that scans a UAB the SAR will wait for a positive edge on the trigger output of that UAB. Caveat: in this mode the length of SAR scan can be variable.

1 (SCHEDULED): Scheduled UABs: All UABs scanned by the SAR are assumed to be properly scheduled, i.e. their output is assumed to be valid when sampled by the SAR and the SAR does not wait. In this mode the length of the SAR scan is constant. This mode requires that the SAR scans strictly periodically, i.e. the SAR has to either run continuously or has to be triggered by a periodic hardware trigger (TCPWM or UDB timer). It also requires that the end of the UAB valid phase is precisely aligned with the end of the SAR sample period (using UAB.STARTUP_DELAY). Normally this scheduling is done by Creator.

REPEAT_INVALID

For unscheduled UAB_SCAN_MODE only, do the following if an invalid sample is received:

  • 0: use the last known valid sample for that channel and clear the NEWVALUE flag
  • 1: repeat the conversions until a valid sample is received (caveat: could be never if the UAB valid window is incorrectly schedule w.r.t. SAR sampling)
VALID_SEL

Static UAB Valid select 0=UAB0 half 0 Valid output 1=UAB0 half 1 Valid output 2=UAB1 half 0 Valid output 3=UAB1 half 1 Valid output 4=UAB2 half 0 Valid output 5=UAB2 half 1 Valid output 6=UAB3 half 0 Valid output 7=UAB3 half 1 Valid output

VALID_SEL_EN

Enable static UAB Valid selection (override Hardware)

VALID_IGNORE

Ignore UAB valid signal, including the dynamic/Hardware from AROUTE and the static Valid selection from the VALID_SEL fields above

TRIGGER_OUT_EN

SAR output trigger enable (used for UAB synchronization). To ensure multiple UABs starting at the same trigger it is recommended to use this bit to temporarily disable the trigger output until all those UABs are set to run (UAB.SRAM_CTRL.RUN=1).

EOS_DSI_OUT_EN

Enable to output EOS_INTR to DSI. When enabled each time EOS_INTR is set by the hardware also a trigger pulse is send on the tr_sar_out signal.

Links

() ()